The present invention relates to circuits.
Programmable logic devices (PLDs) (also sometimes referred to as complex PLDs (CPLDs), programmable array logic (PALs), programmable logic arrays (PLAs), field PLAs (FPLAs), erasable PLDs (EPLDs), electrically erasable PLDs (EEPLDs), logic cell arrays (LCAs), field programmable gate arrays (FPGAs), or by other names), are well-known integrated circuits (ICs) that provide the advantages of fixed ICs with the flexibility of custom ICs. Such devices typically provide an “off the shelf” device having at least a portion that can be programmed to meet a user's specific needs. Application specific integrated circuits (ASICs) have traditionally been fixed ICs. However, it is possible to provide an ASIC that has a portion or portions that are programmable. Thus, it is possible for an IC device to have qualities of both an ASIC and a PLD. The term PLD as used herein will be considered broad enough to include such devices.
PLDs have configuration elements that may be programmed or reprogrammed. Placing new data into the configuration elements programs or reprograms the PLD's logic functions and associated routing pathways. Configuration elements that are field programmable are often implemented as random access memory (RAM) cells, which in PLDs are sometimes referred to a “configuration RAM” (CRAM)). CRAMs are generally implemented as static RAM (SRAM). Thus, CRAMs generally refer to SRAM. As such, the term CRAM is herein used to refer to configuration memory implemented as SRAM. The CRAM is typically arranged in an array of columns and rows of memory cells. Each cell of a CRAM is typically connected to the gate terminal of a corresponding pass gate, which normally acts as a switch connecting a data input terminal to a data output terminal.
CRAMs suffer from a number of disadvantages. First, they are susceptible to soft error upsets (SEUs), which are sometimes referred to as “one-off errors”. The soft error rate (SER) increases as component device sizes are reduced or as voltages applied to the component devices (e.g., VCC) are reduced. As a result, soft errors limit lowering the size of the component devices used in the CRAM or the voltages applied to its component devices. Consequently, larger component devices and higher applied voltages are used. Moreover, at times, layouts that add more capacitance to devices are used, which makes the CRAM less susceptible to soft errors. This complicates the layout process. Second, as CRAMs are volatile memories, each time a PLD is powered on, configuration data must be loaded and stored in the CRAM. This causes undesirable delays in readying the PLD.
One way to correct soft errors in CRAM is to reload the configuration data. This, however, requires interrupting the operation of the PLD. Another technique to correct soft errors is to use multiple redundancy (e.g., triple redundancy). This, in turn, requires using a larger CRAM block. Additionally, both of these methods require use of error detection methods.
Similarly, a multiplexer that uses a CRAM-based look-up-table (LUT) for decoding (e.g., select signals of the multiplexer) also suffers from soft errors and volatility issues discussed above. Also, the performance of the switches in the multiplexer and thus of the multiplexer itself degrades with smaller process nodes used for fabricating devices making up the multiplexer. This is because the supply voltage for smaller process nodes is smaller and because there is a lower limit on reducing the threshold voltage for transistors used as switches in the multiplexer. As a result, scaling down of the process nodes reduces the current through the switches.
Embodiments of the present invention arise in this context.